diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 41e29a6..7f5087a 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -14,7 +14,8 @@
 #include <pci.h>
 
 static const struct udevice_id generic_pch_ids[] = {
-	{ .compatible = "intel,pch" },
+	{ .compatible = "intel,pch7" },
+	{ .compatible = "intel,pch9" },
 	{ }
 };
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..205405b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@
 	struct irq_routing_table *rt;
 	struct irq_info *slot, *slot_base;
 	int irq_entries = 0;
+	int parent;
 	int i;
 	int ret;
 
@@ -106,7 +107,11 @@
 		return -EINVAL;
 	}
 
-	ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+	/* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */
+	parent = fdt_parent_offset(blob, node);
+	if (parent < 0)
+		return -EINVAL;
+	ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
 				  "reg", &addr);
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..c000aca 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
+#include <pch.h>
 #include <asm/lapic.h>
 #include <asm/pci.h>
 #include <asm/arch/bd82x6x.h>
@@ -16,6 +16,8 @@
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
+#define BIOS_CTRL	0xdc
+
 void bd82x6x_pci_init(pci_dev_t dev)
 {
 	u16 reg16;
@@ -96,6 +98,7 @@
 	return 0;
 }
 
+/* TODO(sjg@chromium.org): Move this to the PCH init() method */
 int bd82x6x_init(void)
 {
 	const void *blob = gd->fdt_blob;
@@ -116,6 +119,47 @@
 	return 0;
 }
 
+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+	u32 rcba;
+
+	dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+	rcba = rcba & 0xffffc000;
+	*sbasep = rcba + 0x3800;
+
+	return 0;
+}
+
+static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+{
+	return PCHV_9;
+}
+
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+{
+	uint8_t bios_cntl;
+
+	/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+	dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+	if (protect) {
+		bios_cntl &= ~BIOS_CTRL_BIOSWE;
+		bios_cntl |= BIT(5);
+	} else {
+		bios_cntl |= BIOS_CTRL_BIOSWE;
+		bios_cntl &= ~BIT(5);
+	}
+	dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+	return 0;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+	.get_sbase	= bd82x6x_pch_get_sbase,
+	.get_version	= bd82x6x_pch_get_version,
+	.set_spi_protect = bd82x6x_set_spi_protect,
+};
+
 static const struct udevice_id bd82x6x_ids[] = {
 	{ .compatible = "intel,bd82x6x" },
 	{ }
@@ -126,4 +170,5 @@
 	.id		= UCLASS_PCH,
 	.of_match	= bd82x6x_ids,
 	.probe		= bd82x6x_probe,
+	.ops		= &bd82x6x_pch_ops,
 };
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d3380de..9bf707b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,23 +65,6 @@
 		};
 	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0>;
-			compatible = "winbond,w25q64dw", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				reg = <0x006e0000 0x00010000>;
-			};
-		};
-	};
-
 	gpioa {
 		compatible = "intel,ich6-gpio";
 		u-boot,dm-pre-reloc;
@@ -133,66 +116,91 @@
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
-		irq-router@1f,0 {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "ibase";
-			intel,ibase-offset = <0x50>;
-			intel,pirq-link = <8 8>;
-			intel,pirq-mask = <0xdee0>;
-			intel,pirq-routing = <
-				/* BayTrail PCI devices */
-				PCI_BDF(0, 2, 0) INTA PIRQA
-				PCI_BDF(0, 3, 0) INTA PIRQA
-				PCI_BDF(0, 16, 0) INTA PIRQA
-				PCI_BDF(0, 17, 0) INTA PIRQA
-				PCI_BDF(0, 18, 0) INTA PIRQA
-				PCI_BDF(0, 19, 0) INTA PIRQA
-				PCI_BDF(0, 20, 0) INTA PIRQA
-				PCI_BDF(0, 21, 0) INTA PIRQA
-				PCI_BDF(0, 22, 0) INTA PIRQA
-				PCI_BDF(0, 23, 0) INTA PIRQA
-				PCI_BDF(0, 24, 0) INTA PIRQA
-				PCI_BDF(0, 24, 1) INTC PIRQC
-				PCI_BDF(0, 24, 2) INTD PIRQD
-				PCI_BDF(0, 24, 3) INTB PIRQB
-				PCI_BDF(0, 24, 4) INTA PIRQA
-				PCI_BDF(0, 24, 5) INTC PIRQC
-				PCI_BDF(0, 24, 6) INTD PIRQD
-				PCI_BDF(0, 24, 7) INTB PIRQB
-				PCI_BDF(0, 26, 0) INTA PIRQA
-				PCI_BDF(0, 27, 0) INTA PIRQA
-				PCI_BDF(0, 28, 0) INTA PIRQA
-				PCI_BDF(0, 28, 1) INTB PIRQB
-				PCI_BDF(0, 28, 2) INTC PIRQC
-				PCI_BDF(0, 28, 3) INTD PIRQD
-				PCI_BDF(0, 29, 0) INTA PIRQA
-				PCI_BDF(0, 30, 0) INTA PIRQA
-				PCI_BDF(0, 30, 1) INTD PIRQD
-				PCI_BDF(0, 30, 2) INTB PIRQB
-				PCI_BDF(0, 30, 3) INTC PIRQC
-				PCI_BDF(0, 30, 4) INTD PIRQD
-				PCI_BDF(0, 30, 5) INTB PIRQB
-				PCI_BDF(0, 31, 3) INTB PIRQB
+			compatible = "intel,pch9";
 
-				/* PCIe root ports downstream interrupts */
-				PCI_BDF(1, 0, 0) INTA PIRQA
-				PCI_BDF(1, 0, 0) INTB PIRQB
-				PCI_BDF(1, 0, 0) INTC PIRQC
-				PCI_BDF(1, 0, 0) INTD PIRQD
-				PCI_BDF(2, 0, 0) INTA PIRQB
-				PCI_BDF(2, 0, 0) INTB PIRQC
-				PCI_BDF(2, 0, 0) INTC PIRQD
-				PCI_BDF(2, 0, 0) INTD PIRQA
-				PCI_BDF(3, 0, 0) INTA PIRQC
-				PCI_BDF(3, 0, 0) INTB PIRQD
-				PCI_BDF(3, 0, 0) INTC PIRQA
-				PCI_BDF(3, 0, 0) INTD PIRQB
-				PCI_BDF(4, 0, 0) INTA PIRQD
-				PCI_BDF(4, 0, 0) INTB PIRQA
-				PCI_BDF(4, 0, 0) INTC PIRQB
-				PCI_BDF(4, 0, 0) INTD PIRQC
-			>;
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* BayTrail PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 22, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 1) INTD PIRQD
+					PCI_BDF(0, 30, 2) INTB PIRQB
+					PCI_BDF(0, 30, 3) INTC PIRQC
+					PCI_BDF(0, 30, 4) INTD PIRQD
+					PCI_BDF(0, 30, 5) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64dw",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x006e0000 0x00010000>;
+					};
+				};
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 194f0eb..4e9e410 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -29,16 +29,22 @@
 		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
-	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			reg = <0>;
-			compatible = "winbond,w25q128", "spi-flash";
-			memory-map = <0xff000000 0x01000000>;
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,pch9";
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					reg = <0>;
+					compatible = "winbond,w25q128", "spi-flash";
+					memory-map = <0xff000000 0x01000000>;
+				};
+			};
 		};
 	};
+
 };
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index c4469a9..a5c5dc1 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -186,9 +186,9 @@
 			intel,pch-backlight = <0x04000000>;
 		};
 
-		pch {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,bd82x6x", "intel,pch";
+			compatible = "intel,bd82x6x", "intel,pch9";
 			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -200,6 +200,7 @@
 						1 0 0 0 0 0 0 0>;
 			/* Enable EC SMI source */
 			intel,alt-gp-smi-enable = <0x0100>;
+
 			spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 4e2b517..2302701 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -51,21 +51,27 @@
 		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x1000 0x1000 0 0xf000>;
-	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#size-cells = <1>;
-			#address-cells = <1>;
-			reg = <0>;
-			compatible = "winbond,w25q64", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				reg = <0x003e0000 0x00010000>;
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,pch9";
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+					};
+				};
 			};
 		};
 	};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 84231b3..2a18be0 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -72,17 +72,6 @@
 		stdout-path = "/serial";
 	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			reg = <0>;
-			compatible = "sst,25vf016b", "spi-flash";
-			memory-map = <0xffe00000 0x00200000>;
-		};
-	};
-
 	microcode {
 		update@0 {
 #include "microcode/m0220661105_cv.dtsi"
@@ -170,68 +159,85 @@
 			};
 		};
 
-		irq-router@1f,0 {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "pci";
-			intel,pirq-link = <0x60 8>;
-			intel,pirq-mask = <0xcee0>;
-			intel,pirq-routing = <
-				/* TunnelCreek PCI devices */
-				PCI_BDF(0, 2, 0) INTA PIRQE
-				PCI_BDF(0, 3, 0) INTA PIRQF
-				PCI_BDF(0, 23, 0) INTA PIRQA
-				PCI_BDF(0, 23, 0) INTB PIRQB
-				PCI_BDF(0, 23, 0) INTC PIRQC
-				PCI_BDF(0, 23, 0) INTD PIRQD
-				PCI_BDF(0, 24, 0) INTA PIRQB
-				PCI_BDF(0, 24, 0) INTB PIRQC
-				PCI_BDF(0, 24, 0) INTC PIRQD
-				PCI_BDF(0, 24, 0) INTD PIRQA
-				PCI_BDF(0, 25, 0) INTA PIRQC
-				PCI_BDF(0, 25, 0) INTB PIRQD
-				PCI_BDF(0, 25, 0) INTC PIRQA
-				PCI_BDF(0, 25, 0) INTD PIRQB
-				PCI_BDF(0, 26, 0) INTA PIRQD
-				PCI_BDF(0, 26, 0) INTB PIRQA
-				PCI_BDF(0, 26, 0) INTC PIRQB
-				PCI_BDF(0, 26, 0) INTD PIRQC
-				PCI_BDF(0, 27, 0) INTA PIRQG
-				/*
-				 * Topcliff PCI devices
-				 *
-				 * Note on the Crown Bay board, Topcliff chipset
-				 * is connected to TunnelCreek PCIe port 0, so
-				 * its bus number is 1 for its PCIe port and 2
-				 * for its PCI devices per U-Boot current PCI
-				 * bus enumeration algorithm.
-				 */
-				PCI_BDF(1, 0, 0) INTA PIRQA
-				PCI_BDF(2, 0, 1) INTA PIRQA
-				PCI_BDF(2, 0, 2) INTA PIRQA
-				PCI_BDF(2, 2, 0) INTB PIRQD
-				PCI_BDF(2, 2, 1) INTB PIRQD
-				PCI_BDF(2, 2, 2) INTB PIRQD
-				PCI_BDF(2, 2, 3) INTB PIRQD
-				PCI_BDF(2, 2, 4) INTB PIRQD
-				PCI_BDF(2, 4, 0) INTC PIRQC
-				PCI_BDF(2, 4, 1) INTC PIRQC
-				PCI_BDF(2, 6, 0) INTD PIRQB
-				PCI_BDF(2, 8, 0) INTA PIRQA
-				PCI_BDF(2, 8, 1) INTA PIRQA
-				PCI_BDF(2, 8, 2) INTA PIRQA
-				PCI_BDF(2, 8, 3) INTA PIRQA
-				PCI_BDF(2, 10, 0) INTB PIRQD
-				PCI_BDF(2, 10, 1) INTB PIRQD
-				PCI_BDF(2, 10, 2) INTB PIRQD
-				PCI_BDF(2, 10, 3) INTB PIRQD
-				PCI_BDF(2, 10, 4) INTB PIRQD
-				PCI_BDF(2, 12, 0) INTC PIRQC
-				PCI_BDF(2, 12, 1) INTC PIRQC
-				PCI_BDF(2, 12, 2) INTC PIRQC
-				PCI_BDF(2, 12, 3) INTC PIRQC
-				PCI_BDF(2, 12, 4) INTC PIRQC
-			>;
+			compatible = "intel,pch7";
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "pci";
+				intel,pirq-link = <0x60 8>;
+				intel,pirq-mask = <0xcee0>;
+				intel,pirq-routing = <
+					/* TunnelCreek PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQE
+					PCI_BDF(0, 3, 0) INTA PIRQF
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTB PIRQB
+					PCI_BDF(0, 23, 0) INTC PIRQC
+					PCI_BDF(0, 23, 0) INTD PIRQD
+					PCI_BDF(0, 24, 0) INTA PIRQB
+					PCI_BDF(0, 24, 0) INTB PIRQC
+					PCI_BDF(0, 24, 0) INTC PIRQD
+					PCI_BDF(0, 24, 0) INTD PIRQA
+					PCI_BDF(0, 25, 0) INTA PIRQC
+					PCI_BDF(0, 25, 0) INTB PIRQD
+					PCI_BDF(0, 25, 0) INTC PIRQA
+					PCI_BDF(0, 25, 0) INTD PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQD
+					PCI_BDF(0, 26, 0) INTB PIRQA
+					PCI_BDF(0, 26, 0) INTC PIRQB
+					PCI_BDF(0, 26, 0) INTD PIRQC
+					PCI_BDF(0, 27, 0) INTA PIRQG
+					/*
+					* Topcliff PCI devices
+					*
+					* Note on the Crown Bay board, Topcliff
+					* chipset is connected to TunnelCreek
+					* PCIe port 0, so its bus number is 1
+					* for its PCIe port and 2 for its PCI
+					* devices per U-Boot current PCI bus
+					* enumeration algorithm.
+					*/
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(2, 0, 1) INTA PIRQA
+					PCI_BDF(2, 0, 2) INTA PIRQA
+					PCI_BDF(2, 2, 0) INTB PIRQD
+					PCI_BDF(2, 2, 1) INTB PIRQD
+					PCI_BDF(2, 2, 2) INTB PIRQD
+					PCI_BDF(2, 2, 3) INTB PIRQD
+					PCI_BDF(2, 2, 4) INTB PIRQD
+					PCI_BDF(2, 4, 0) INTC PIRQC
+					PCI_BDF(2, 4, 1) INTC PIRQC
+					PCI_BDF(2, 6, 0) INTD PIRQB
+					PCI_BDF(2, 8, 0) INTA PIRQA
+					PCI_BDF(2, 8, 1) INTA PIRQA
+					PCI_BDF(2, 8, 2) INTA PIRQA
+					PCI_BDF(2, 8, 3) INTA PIRQA
+					PCI_BDF(2, 10, 0) INTB PIRQD
+					PCI_BDF(2, 10, 1) INTB PIRQD
+					PCI_BDF(2, 10, 2) INTB PIRQD
+					PCI_BDF(2, 10, 3) INTB PIRQD
+					PCI_BDF(2, 10, 4) INTB PIRQD
+					PCI_BDF(2, 12, 0) INTC PIRQC
+					PCI_BDF(2, 12, 1) INTC PIRQC
+					PCI_BDF(2, 12, 2) INTC PIRQC
+					PCI_BDF(2, 12, 3) INTC PIRQC
+					PCI_BDF(2, 12, 4) INTC PIRQC
+				>;
+			};
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					reg = <0>;
+					compatible = "sst,25vf016b",
+						"spi-flash";
+					memory-map = <0xffe00000 0x00200000>;
+				};
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 55165e1..9d82bb3 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -79,37 +79,59 @@
 			current-speed = <115200>;
 		};
 
-		irq-router@1f,0 {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "pci";
-			intel,pirq-link = <0x60 8>;
-			intel,pirq-mask = <0xdef8>;
-			intel,pirq-routing = <
-				PCI_BDF(0, 20, 0) INTA PIRQE
-				PCI_BDF(0, 20, 1) INTB PIRQF
-				PCI_BDF(0, 20, 2) INTC PIRQG
-				PCI_BDF(0, 20, 3) INTD PIRQH
-				PCI_BDF(0, 20, 4) INTA PIRQE
-				PCI_BDF(0, 20, 5) INTB PIRQF
-				PCI_BDF(0, 20, 6) INTC PIRQG
-				PCI_BDF(0, 20, 7) INTD PIRQH
-				PCI_BDF(0, 21, 0) INTA PIRQE
-				PCI_BDF(0, 21, 1) INTB PIRQF
-				PCI_BDF(0, 21, 2) INTC PIRQG
-				PCI_BDF(0, 23, 0) INTA PIRQA
-				PCI_BDF(0, 23, 1) INTB PIRQB
+			compatible = "intel,pch7";
 
-				/* PCIe root ports downstream interrupts */
-				PCI_BDF(1, 0, 0) INTA PIRQA
-				PCI_BDF(1, 0, 0) INTB PIRQB
-				PCI_BDF(1, 0, 0) INTC PIRQC
-				PCI_BDF(1, 0, 0) INTD PIRQD
-				PCI_BDF(2, 0, 0) INTA PIRQB
-				PCI_BDF(2, 0, 0) INTB PIRQC
-				PCI_BDF(2, 0, 0) INTC PIRQD
-				PCI_BDF(2, 0, 0) INTD PIRQA
-			>;
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "pci";
+				intel,pirq-link = <0x60 8>;
+				intel,pirq-mask = <0xdef8>;
+				intel,pirq-routing = <
+					PCI_BDF(0, 20, 0) INTA PIRQE
+					PCI_BDF(0, 20, 1) INTB PIRQF
+					PCI_BDF(0, 20, 2) INTC PIRQG
+					PCI_BDF(0, 20, 3) INTD PIRQH
+					PCI_BDF(0, 20, 4) INTA PIRQE
+					PCI_BDF(0, 20, 5) INTB PIRQF
+					PCI_BDF(0, 20, 6) INTC PIRQG
+					PCI_BDF(0, 20, 7) INTD PIRQH
+					PCI_BDF(0, 21, 0) INTA PIRQE
+					PCI_BDF(0, 21, 1) INTB PIRQF
+					PCI_BDF(0, 21, 2) INTC PIRQG
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 23, 1) INTB PIRQB
+
+					/* PCIe root ports downstream interrupts */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+				>;
+			};
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x00010000 0x00010000>;
+					};
+				};
+			};
 		};
 	};
 
@@ -127,21 +149,4 @@
 		bank-name = "B";
 	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#size-cells = <1>;
-			#address-cells = <1>;
-			reg = <0>;
-			compatible = "winbond,w25q64", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				reg = <0x00010000 0x00010000>;
-			};
-		};
-	};
-
 };
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bbfd6d4..e7ef7c9 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -150,66 +150,91 @@
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
-		irq-router@1f,0 {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "ibase";
-			intel,ibase-offset = <0x50>;
-			intel,pirq-link = <8 8>;
-			intel,pirq-mask = <0xdee0>;
-			intel,pirq-routing = <
-				/* BayTrail PCI devices */
-				PCI_BDF(0, 2, 0) INTA PIRQA
-				PCI_BDF(0, 3, 0) INTA PIRQA
-				PCI_BDF(0, 16, 0) INTA PIRQA
-				PCI_BDF(0, 17, 0) INTA PIRQA
-				PCI_BDF(0, 18, 0) INTA PIRQA
-				PCI_BDF(0, 19, 0) INTA PIRQA
-				PCI_BDF(0, 20, 0) INTA PIRQA
-				PCI_BDF(0, 21, 0) INTA PIRQA
-				PCI_BDF(0, 22, 0) INTA PIRQA
-				PCI_BDF(0, 23, 0) INTA PIRQA
-				PCI_BDF(0, 24, 0) INTA PIRQA
-				PCI_BDF(0, 24, 1) INTC PIRQC
-				PCI_BDF(0, 24, 2) INTD PIRQD
-				PCI_BDF(0, 24, 3) INTB PIRQB
-				PCI_BDF(0, 24, 4) INTA PIRQA
-				PCI_BDF(0, 24, 5) INTC PIRQC
-				PCI_BDF(0, 24, 6) INTD PIRQD
-				PCI_BDF(0, 24, 7) INTB PIRQB
-				PCI_BDF(0, 26, 0) INTA PIRQA
-				PCI_BDF(0, 27, 0) INTA PIRQA
-				PCI_BDF(0, 28, 0) INTA PIRQA
-				PCI_BDF(0, 28, 1) INTB PIRQB
-				PCI_BDF(0, 28, 2) INTC PIRQC
-				PCI_BDF(0, 28, 3) INTD PIRQD
-				PCI_BDF(0, 29, 0) INTA PIRQA
-				PCI_BDF(0, 30, 0) INTA PIRQA
-				PCI_BDF(0, 30, 1) INTD PIRQD
-				PCI_BDF(0, 30, 2) INTB PIRQB
-				PCI_BDF(0, 30, 3) INTC PIRQC
-				PCI_BDF(0, 30, 4) INTD PIRQD
-				PCI_BDF(0, 30, 5) INTB PIRQB
-				PCI_BDF(0, 31, 3) INTB PIRQB
+			compatible = "pci8086,0f1c", "intel,pch9";
 
-				/* PCIe root ports downstream interrupts */
-				PCI_BDF(1, 0, 0) INTA PIRQA
-				PCI_BDF(1, 0, 0) INTB PIRQB
-				PCI_BDF(1, 0, 0) INTC PIRQC
-				PCI_BDF(1, 0, 0) INTD PIRQD
-				PCI_BDF(2, 0, 0) INTA PIRQB
-				PCI_BDF(2, 0, 0) INTB PIRQC
-				PCI_BDF(2, 0, 0) INTC PIRQD
-				PCI_BDF(2, 0, 0) INTD PIRQA
-				PCI_BDF(3, 0, 0) INTA PIRQC
-				PCI_BDF(3, 0, 0) INTB PIRQD
-				PCI_BDF(3, 0, 0) INTC PIRQA
-				PCI_BDF(3, 0, 0) INTD PIRQB
-				PCI_BDF(4, 0, 0) INTA PIRQD
-				PCI_BDF(4, 0, 0) INTB PIRQA
-				PCI_BDF(4, 0, 0) INTC PIRQB
-				PCI_BDF(4, 0, 0) INTD PIRQC
-			>;
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* BayTrail PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 22, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 1) INTD PIRQD
+					PCI_BDF(0, 30, 2) INTB PIRQB
+					PCI_BDF(0, 30, 3) INTC PIRQC
+					PCI_BDF(0, 30, 4) INTD PIRQD
+					PCI_BDF(0, 30, 5) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "stmicro,n25q064a",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x006f0000 0x00010000>;
+					};
+				};
+			};
 		};
 	};
 
@@ -269,23 +294,6 @@
 		};
 	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0>;
-			compatible = "stmicro,n25q064a", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				reg = <0x006f0000 0x00010000>;
-			};
-		};
-	};
-
 	microcode {
 		update@0 {
 #include "microcode/m0130673322.dtsi"
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 9086b46..9c3f2a0 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -51,18 +51,22 @@
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
-		irq-router@1,0 {
+		pch@1,0 {
 			reg = <0x00000800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "pci";
-			intel,pirq-link = <0x60 4>;
-			intel,pirq-mask = <0x0e40>;
-			intel,pirq-routing = <
-				/* PIIX UHCI */
-				PCI_BDF(0, 1, 2) INTD PIRQD
-				/* e1000 NIC */
-				PCI_BDF(0, 3, 0) INTA PIRQC
-			>;
+			compatible = "intel,pch7";
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "pci";
+				intel,pirq-link = <0x60 4>;
+				intel,pirq-mask = <0x0e40>;
+				intel,pirq-routing = <
+					/* PIIX UHCI */
+					PCI_BDF(0, 1, 2) INTD PIRQD
+					/* e1000 NIC */
+					PCI_BDF(0, 3, 0) INTA PIRQC
+				>;
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 145e811..5d601b3 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -62,24 +62,28 @@
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
-		irq-router@1f,0 {
+		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,irq-router";
-			intel,pirq-config = "pci";
-			intel,pirq-link = <0x60 8>;
-			intel,pirq-mask = <0x0e40>;
-			intel,pirq-routing = <
-				/* e1000 NIC */
-				PCI_BDF(0, 2, 0) INTA PIRQG
-				/* ICH9 UHCI */
-				PCI_BDF(0, 29, 0) INTA PIRQA
-				PCI_BDF(0, 29, 1) INTB PIRQB
-				PCI_BDF(0, 29, 2) INTC PIRQC
-				/* ICH9 EHCI */
-				PCI_BDF(0, 29, 7) INTD PIRQD
-				/* ICH9 SATA */
-				PCI_BDF(0, 31, 2) INTA PIRQA
-			>;
+			compatible = "intel,pch9";
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "pci";
+				intel,pirq-link = <0x60 8>;
+				intel,pirq-mask = <0x0e40>;
+				intel,pirq-routing = <
+					/* e1000 NIC */
+					PCI_BDF(0, 2, 0) INTA PIRQG
+					/* ICH9 UHCI */
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 29, 1) INTB PIRQB
+					PCI_BDF(0, 29, 2) INTC PIRQC
+					/* ICH9 EHCI */
+					PCI_BDF(0, 29, 7) INTD PIRQD
+					/* ICH9 SATA */
+					PCI_BDF(0, 31, 2) INTA PIRQA
+				>;
+			};
 		};
 	};
 
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 887510b..e543b8f 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -5,14 +5,14 @@
  *
  * This file is derived from the flashrom project.
  */
-
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
-#include <spi.h>
+#include <pch.h>
 #include <pci.h>
 #include <pci_ids.h>
+#include <spi.h>
 #include <asm/io.h>
 
 #include "ich.h"
@@ -27,9 +27,7 @@
 #endif
 
 struct ich_spi_platdata {
-	pci_dev_t dev;		/* PCI device number */
-	int ich_version;	/* Controller version, 7 or 9 */
-	bool use_sbase;		/* Use SBASE instead of RCB */
+	enum pch_version ich_version;	/* Controller version, 7 or 9 */
 };
 
 struct ich_spi_priv {
@@ -122,40 +120,16 @@
 	ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
 }
 
-/*
- * Check if this device ID matches one of supported Intel PCH devices.
- *
- * Return the ICH version if there is a match, or zero otherwise.
- */
-static int get_ich_version(uint16_t device_id)
-{
-	if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
-	    device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
-	    device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
-		return 7;
-
-	if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
-	     device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
-	    (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
-	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
-	    device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
-	    device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC ||
-	    device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC)
-		return 9;
-
-	return 0;
-}
-
 /* @return 1 if the SPI flash supports the 33MHz speed */
-static int ich9_can_do_33mhz(pci_dev_t dev)
+static int ich9_can_do_33mhz(struct udevice *dev)
 {
 	u32 fdod, speed;
 
 	/* Observe SPI Descriptor Component Section 0 */
-	pci_write_config_dword(dev, 0xb0, 0x1000);
+	dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
 
 	/* Extract the Write/Erase SPI Frequency from descriptor */
-	pci_read_config_dword(dev, 0xb4, &fdod);
+	dm_pci_read_config32(dev->parent, 0xb4, &fdod);
 
 	/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
 	speed = (fdod >> 21) & 7;
@@ -163,59 +137,22 @@
 	return speed == 1;
 }
 
-static int ich_find_spi_controller(struct ich_spi_platdata *ich)
-{
-	int last_bus = pci_last_busno();
-	int bus;
-
-	if (last_bus == -1) {
-		debug("No PCI busses?\n");
-		return -ENODEV;
-	}
-
-	for (bus = 0; bus <= last_bus; bus++) {
-		uint16_t vendor_id, device_id;
-		uint32_t ids;
-		pci_dev_t dev;
-
-		dev = PCI_BDF(bus, 31, 0);
-		pci_read_config_dword(dev, 0, &ids);
-		vendor_id = ids;
-		device_id = ids >> 16;
-
-		if (vendor_id == PCI_VENDOR_ID_INTEL) {
-			ich->dev = dev;
-			ich->ich_version = get_ich_version(device_id);
-			if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
-				ich->use_sbase = true;
-			return ich->ich_version == 0 ? -ENODEV : 0;
-		}
-	}
-
-	debug("ICH SPI: No ICH found.\n");
-	return -ENODEV;
-}
-
-static int ich_init_controller(struct ich_spi_platdata *plat,
+static int ich_init_controller(struct udevice *dev,
+			       struct ich_spi_platdata *plat,
 			       struct ich_spi_priv *ctlr)
 {
-	uint8_t *rcrb; /* Root Complex Register Block */
-	uint32_t rcba; /* Root Complex Base Address */
-	uint32_t sbase_addr;
-	uint8_t *sbase;
-
-	pci_read_config_dword(plat->dev, 0xf0, &rcba);
-	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
-	rcrb = (uint8_t *)(rcba & 0xffffc000);
+	ulong sbase_addr;
+	void *sbase;
 
 	/* SBASE is similar */
-	pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
-	sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
+	pch_get_sbase(dev->parent, &sbase_addr);
+	sbase = (void *)sbase_addr;
+	debug("%s: sbase=%p\n", __func__, sbase);
 
-	if (plat->ich_version == 7) {
-		struct ich7_spi_regs *ich7_spi;
+	if (plat->ich_version == PCHV_7) {
+		struct ich7_spi_regs *ich7_spi = sbase;
 
-		ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
+		ich7_spi = (struct ich7_spi_regs *)sbase;
 		ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
 		ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
 		ctlr->menubytes = sizeof(ich7_spi->opmenu);
@@ -228,13 +165,9 @@
 		ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
 		ctlr->preop = offsetof(struct ich7_spi_regs, preop);
 		ctlr->base = ich7_spi;
-	} else if (plat->ich_version == 9) {
-		struct ich9_spi_regs *ich9_spi;
+	} else if (plat->ich_version == PCHV_9) {
+		struct ich9_spi_regs *ich9_spi = sbase;
 
-		if (plat->use_sbase)
-			ich9_spi = (struct ich9_spi_regs *)sbase;
-		else
-			ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
 		ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
 		ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
 		ctlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -258,9 +191,9 @@
 
 	/* Work out the maximum speed we can support */
 	ctlr->max_speed = 20000000;
-	if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
+	if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
 		ctlr->max_speed = 33000000;
-	debug("ICH SPI: Version %d detected at %p, speed %ld\n",
+	debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
 	      plat->ich_version, ctlr->base, ctlr->max_speed);
 
 	ich_set_bbar(ctlr, 0);
@@ -487,7 +420,7 @@
 	if (ret < 0)
 		return ret;
 
-	if (plat->ich_version == 7)
+	if (plat->ich_version == PCHV_7)
 		ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 	else
 		ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
@@ -682,30 +615,30 @@
 	return 0;
 }
 
-static int ich_spi_probe(struct udevice *bus)
+static int ich_spi_probe(struct udevice *dev)
 {
-	struct ich_spi_platdata *plat = dev_get_platdata(bus);
-	struct ich_spi_priv *priv = dev_get_priv(bus);
+	struct ich_spi_platdata *plat = dev_get_platdata(dev);
+	struct ich_spi_priv *priv = dev_get_priv(dev);
 	uint8_t bios_cntl;
 	int ret;
 
-	ret = ich_init_controller(plat, priv);
+	/* Check the ICH version */
+	plat->ich_version = pch_get_version(dev->parent);
+
+	ret = ich_init_controller(dev, plat, priv);
 	if (ret)
 		return ret;
-	/*
-	 * Disable the BIOS write protect so write commands are allowed.  On
-	 * v9, deassert SMM BIOS Write Protect Disable.
-	 */
-	if (plat->use_sbase) {
+	/* Disable the BIOS write protect so write commands are allowed */
+	ret = pch_set_spi_protect(dev->parent, false);
+	if (ret == -ENOSYS) {
 		bios_cntl = ich_readb(priv, priv->bcr);
 		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
 		ich_writeb(priv, bios_cntl, priv->bcr);
-	} else {
-		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
-		if (plat->ich_version == 9)
-			bios_cntl &= ~BIT(5);
-		pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
+	} else if (ret) {
+		debug("%s: Failed to disable write-protect: err=%d\n",
+		      __func__, ret);
+		return ret;
 	}
 
 	priv->cur_speed = priv->max_speed;
@@ -713,18 +646,6 @@
 	return 0;
 }
 
-static int ich_spi_ofdata_to_platdata(struct udevice *bus)
-{
-	struct ich_spi_platdata *plat = dev_get_platdata(bus);
-	int ret;
-
-	ret = ich_find_spi_controller(plat);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 static int ich_spi_set_speed(struct udevice *bus, uint speed)
 {
 	struct ich_spi_priv *priv = dev_get_priv(bus);
@@ -757,7 +678,7 @@
 	 * ICH 7 SPI controller only supports array read command
 	 * and byte program command for SST flash
 	 */
-	if (plat->ich_version == 7) {
+	if (plat->ich_version == PCHV_7) {
 		slave->mode_rx = SPI_RX_SLOW;
 		slave->mode = SPI_TX_BYTE;
 	}
@@ -785,7 +706,6 @@
 	.id	= UCLASS_SPI,
 	.of_match = ich_spi_ids,
 	.ops	= &ich_spi_ops,
-	.ofdata_to_platdata = ich_spi_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
 	.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
 	.child_pre_probe = ich_spi_child_pre_probe,